DocumentCode
1769113
Title
A spare router based reliable Network-on-Chip design
Author
Chatterjee, Niladrish ; Chattopadhyay, Subrata ; Manna, Kanchan
Author_Institution
Indian Inst. of Technol., Electron. & Electr. Commun. Eng., Kharagpur, India
fYear
2014
fDate
1-5 June 2014
Firstpage
1957
Lastpage
1960
Abstract
This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability, mean time to failure (MTTF) and area overhead with existing works. For a 10 × 10 mesh, it gives a 1.14 reliability gain over quad-spare mesh, 1.42 reliability gain over column-spare mesh and 21.195 reliability gain over normal mesh. The mean time to failure (MTTF) gains over column-spare, quad spare and normal mesh are 3.19, 7.51, and 33.38 respectively. We have also presented a system performance report which includes throughput and latency of the proposed design.
Keywords
network routing; network topology; network-on-chip; MTTF; NoC; mean time to failure; network-on-chip design; router redundancy; routing algorithm; Circuit faults; Fault tolerant systems; Redundancy; Routing; Topology; Fault Tolerance; Network-on-Chip; Reconfigurable; Spare Router;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location
Melbourne VIC
Print_ISBN
978-1-4799-3431-7
Type
conf
DOI
10.1109/ISCAS.2014.6865545
Filename
6865545
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