A method of FPGA interconnect resources testing by using XDL-based configuration

FPGA is widely used in military and aerospace applications and FPGA testing is the most effective means to ensure the reliability of them. Interconnect Resources testing is one of the most important parts of FPGA testing since that most of the faults occur on Interconnect Resources. FPGA needs to be configured as specified circuits before being tested and conventional HDL-based configuration can not achieve controllability of the resources to be tested. In order to solve this problem, we propose a XDL-based configuration. In this paper, grammar and design flow of XDL were analyzed firstly. Then structure of interconnect resources of Xilinx Spartan-3 FPGA and their description using XDL were studied. According to the structure of the interconnect resources, a BIST structure was built to implement the test of them. Through C++ programming, we got XDL programs automatically. With four configurations, we implemented the testing of hex lines across CLBs and not across CLBs as well as double line across CLBs and not across CLBs. The method could solve the problem of uncontrollability of the resources to be tested efficiently.