An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS

Author

Xiaodong Liu ; Andersson, Mats ; Anderson, Matthew ; Sundstrom, Lars ; Andreani, Pietro

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2014

fDate

1-5 June 2014

Firstpage

2337

Lastpage

2340

Abstract

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

Keywords

CMOS integrated circuits; cellular radio; continuous time filters; delta-sigma modulation; thermal noise; CMOS; SNDR/SFDR; bandwidth 20 MHz; cellular communication; clock jitter sensitivity; continuous time delta-sigma modulator; current-steering DAC; frequency 640 MHz; internal quantizer; nonreturn-to-zero DAC pulse; power 11 mW; single loop filter; size 65 nm; thermal noise; voltage 1.2 V; Bandwidth; CMOS integrated circuits; Clocks; Modulation; Noise; Optical signal processing; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865640

Filename

6865640