A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm² in 0.18-μm CMOS process.