A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier

This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparators´s input referred offset. The proposed mismatch suppression is achieved by sampling the mismatches at the dynamic preamplifier´s output node during the precharge phase. A time-domain analysis method is utilized to quantize the suppression effects. By the techniques, a 1-GS/s four-input comparator is implemented by 65-nm CMOS technology. It achieves a 60-μW power dissipation and a 1.89-mV 1-sigma(σ) offset voltage, which is a 90% improvement compared to its non-suppressed counterparts.