Reconfigurable DSP block design for dynamically reconfigurable architecture

Reconfigurable architectures, such as Field-Programmable Gate Arrays (FPGAs), have become one of the key digital circuit implementation platform over the last decade due to its short time-to-market and low design cost. However, the major bottlenecks of FPGAs are their low logic utilization rate and long reconfiguration latency. In order to overcome these limitations, novel dynamically reconfigurable architectures, such as NATURE architecture, have been proposed. It enables runtime reconfiguration and reuse of hardware resources. Significant improvements on logic density, power reduction and reconfiguration flexibility are achieved. However, the previous architectures mainly focus on fine-grain logic. Since modern FPGAs are widely used in computation intensive applications, coarse-grain DSP blocks are needed to further enhance the performance. In this paper, we propose the design of a dynamically reconfigurable DSP block, which can be run-time reconfigured to implement different arithmetic functions in different clock cycles. We first demonstrate its efficiency through implementing typical DSP functions. Then based on NATURE design, simulations on seven benchmarks are performed to show that with DSP blocks, the performance is improved by 58.6% compared to fine-grain NATURE architecture. Then we demonstrate the efficiency reduction of DSP block number by enabling run-time reconfiguration.