Title :
High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems
Author :
Yu-Min Lin ; Yu-Hao Chen ; Ming-Han Chung ; An-Yeu Wu
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a high-throughput layered min-sum quasi-cyclic LDPC (QC-LDPC) decoder for non-volatile memory systems (NVMs). A cost-effective column-based early termination (CB-ET) scheme is proposed to early terminate decoding process within iteration. The throughput improvement is 37.7% compared to the state-of-the-art early termination scheme when raw bit error rate of flash memory is 3×10-3. The QC-LDPC decoder with proposed early termination scheme is synthesized by TSMC 90nm CMOS technology, and the area overhead is only 2.20%.
Keywords :
CMOS memory circuits; cyclic codes; decoding; parity check codes; random-access storage; CMOS technology; High throughput QC-LDPC decoder; cost effective early termination; layered min-sum quasicyclic LDPC decoder; low density parity check code; nonvolatile memory systems; size 90 nm; Bit error rate; Decoding; Flash memories; Iterative decoding; Nonvolatile memory; Throughput; Early termination scheme; Non-volatile memory; layered LDPC decoder;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865738
