Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks

This paper proposes a new architecture that multiplexes both data and clock on serial links, reduces Inter symbol interference (ISI) by using a resistive termination technique, and uses two-level Manchester encoding to solve the reduced swing problem and enable the use of power efficient circuitry. Using this signaling scheme makes the system insensitive to jitter accumulation along the transmission line, and avoids the need for a power hungry clock and data recovery (CDR) circuit. A self-calibrating digital-delay line is also implemented inside the decoder to enable the system to operate efficiently across process, voltage and temperature variations. The proposed scheme is implemented for a 3mm long on-chip transmission line in TSMC 65nm technology and simulation results are presented.