Analysis of RLC interconnect delay model using second order approximation

Continuous scaling of CMOS technology leads to extremely fast device. However, the resulting interconnect structures impose so much parasitic effects that the advantage of ultra-high-speed nanoscale transistors would be completely overshadowed if appropriate remedial steps are not taken. This requires accurate and efficient estimation of interconnect parasitics and analysis of their impacts on integrated circuit performance. This paper proposes a delay model for RLC distributed interconnect network in CMOS technology based on second order approximate transfer function. In addition, this paper also analyzes the time domain output response for two cases of input signals - 1) exponential input signal and 2) approximate periodic ramp input signal.