How much time does FET scaling have left?

The ultimate end of CMOS scaling was predicted almost immediately after the now ubiquitous technology was invented by Frank Wanlass in 1963 [1]. Indeed, many possible limitations to downscaling were discussed in the 1970s, 80s, and 90s [2]. In 2003, Zhirnov et al. [3] estimated the minimal feature size of a “binary logic switch” to be around 1.5nm, based on the Heisenberg uncertainty and Landauer principles. Since then, there have been many papers [2,4,5] discussing the likely end of CMOS scaling due to lithographical, power-thermal, material, and other technological, as opposed to fundamental physical, limitations. In this work, we compute the device switching energy, C_gV_g², for several representative FinFET/MuGFET devices, and explore the role of this quantity as a fundamental physical scaling limitation, which we predict will occur around 2030. In doing so, ITRS downscaling projection data [6] is utilized for reference. MuGFET switching energies are plotted as the blue curve in Fig. 1, in units of 100kBT (T=300K), as FET gate lengths are scaled to 6-nm and below. The inset of Fig. 1 represents our extrapolation of ITRS data. This new way of plotting switching energy reveals that as gate lengths arescaled below about 5nm, the switching energy approaches that of thermal fluctuations.