A 10ps 500MS/s two-channel Vernier TDC in 0.18um CMOS technology

This paper describes a fine resolution, good linearity, and high throughput time-to-digital converter (TDC), which has realized in 0.18um CMOS technology. Based on a two-channel Vernier delay line (VDL) structure and an asynchronous pipelined readout circuitry, the TDC can achieve a maximum throughput of 500MS/s, a time resolution of 10ps and a total conversion range of 640ps. The proposed architecture decreases the length of a single delay line, which improves the integral non-linearity (INL) of TDC. A test block circuit is embedded in the TDC to generate different time interval to facilitate the measurement. The TDC has been taped out with a total area including I/O pads of 1.25×0.675mm².