A compression-based morphable PCM architecture for improving resistance drift tolerance

Due to the growing demand for large memories, using emerging technologies such as Phase Change Memories (PCM) are inevitable. PCM with appropriate scalability, power consumption and multiple bits per cell storage capability is a probable candidate for substituting DRAM. Although storing multiple bits per cell seems to be a rational response to large memory demands, there is a significant problem to achieve this goal. Resistance drift problem is an important reliability concern that is coupled to a multi-level cell PCM (MLC PCM) memory system. In this paper, we propose a memory system architecture that, by exploiting the benefits of compression, converts resistance drift prone blocks to drift resilient blocks in order to protect the memory system from resistance drift. Evaluations on a full-system simulator, consisting of a quad-core ALPHA CMP and a banked PCM memory, show that our proposed approach provides up to 9.8× reduction in bit error rate, an average of 8% reduction in energy consumption, and 21% IPC improvement.