Design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications

A hybrid pixel detector operating in a single photon counting mode requires a pixel readout chip with the geometry that matches the geometry of the detector array. Stringent and growing requirements on smaller pixel size, higher data throughput and more sophisticated functionality are imposed for such imaging systems. CMOS nanometer or 3D technologies seem to be very attractive for pixel readout integrated circuits, especially in the case of implementing more complex functionality or advanced algorithms on the chip. However, these technologies are mainly driven by high density and very fast digital circuits, nevertheless in case of hybrid pixel detectors the analog performance of front-end electronics, such as noise, offset spreads or crosstalk minimization, are of primary importance. We will present some examples of our realization of these kind of ICs both in advance technologies (like 3D or 40 nm CMOS), as well as for commercial application where final yield is of primary importance.