BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

Author

Jordans, Roel ; Diken, Erkan ; Jozwiak, Lech ; Corporaal, Henk

Author_Institution

Dept. of Electr. Eng., Eindhoven Univ. of Technol., Eindhoven, Netherlands

fYear

2014

fDate

23-25 April 2014

Firstpage

83

Lastpage

88

Abstract

In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.

Keywords

application specific integrated circuits; electronic design automation; instruction sets; multiprocessing systems; parallel architectures; ASIP architecture exploration; BuildMaster framework; application specific VLIW processors; application-specific instruction-set processors; compilation; design space exploration; simulation result caching; Computational modeling; Computer architecture; Estimation; Program processors; Prototypes; Radio frequency; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on

Conference_Location

Warsaw

Print_ISBN

978-1-4799-4560-3

Type

conf

DOI

10.1109/DDECS.2014.6868768

Filename

6868768