Timing-aware ATPG for critical paths with multiple TSVs

Author

Metzler, C. ; Todri-Sanial, Aida ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Virazel, A.

Author_Institution

LIRMM, Univ. of Montpellier, Montpellier, France

fYear

2014

fDate

23-25 April 2014

Firstpage

116

Lastpage

121

Abstract

Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.

Keywords

automatic test pattern generation; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D integration technology; 3D-IC reliability; IR-drop; SDF detectability; SDQL metric; TSV testing quality; commercial ATPG tools; critical paths; defective TSVs; electrical conditions; multiple TSVs; path delay variations; small delay faults; small delay variations; statistical delay quality level; test patterns; through-silicon-vias; timing-aware ATPG; Automatic test pattern generation; Circuit faults; Delays; Three-dimensional displays; Through-silicon vias; 3D integration; Through-Silicon vias; resistive open defects; small-delay faults; statistical delay quality level;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on

Conference_Location

Warsaw

Print_ISBN

978-1-4799-4560-3

Type

conf

DOI

10.1109/DDECS.2014.6868774

Filename

6868774