Title :
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips
Author :
Roy, Pranab ; Rahaman, Hafizur ; Dasgupta, Parthasarathi
Author_Institution :
Sch. of VLSI Technol., Bengal Eng. & Sci. Univ., Shibpur, India
Abstract :
Digital microfluidic biochips in recent years have been developed as a major alternative platform for conventional benchtop laboratory procedures. It offers better precision, scalability, higher sensitivity, lower cost due to smaller sample and reagent volumes. Testing of DMFBs is of major significance in terms of dependability and reliability issues for safety-critical applications. A series of complex microfluidic operations are executed in a compact 2D array within a DMFB. The layout engages a group of cells as transportation path as well as a specific cluster of cells as functional modules to perform basic operations of routing, mixing, splitting, merging, storage and detection. In order to determine the correctness and reliability of results testing of these prescheduled layout are necessary both for transportation (structural) as well as functionality (functional). In this paper we propose a technique for customized testing of a prescheduled layout within a microfluidic array. The test performs both structural as well as functional testing for specified cells that forms the layout. The simulations are carried out in testbenches of benchmark suite III and the results are compared with contemporary methods.
Keywords :
bioMEMS; biological techniques; lab-on-a-chip; microfluidics; reliability; DMFB testing; benchmark suite III; compact 2D array; functional testing; layout based customized testing technique; microfluidic array; microfluidic biochips; prescheduled layout testing; reliability; safety-critical applications; total microfluidic operations; transportation path; Arrays; Circuit faults; Electrodes; Layout; Microfluidics; Sensors; Testing; algorithms; customized testing; digital microfluidics; fault diagnosis and detection; routing; structural and functional testing; test completion time; test resource optimization;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location :
Warsaw
Print_ISBN :
978-1-4799-4560-3
DOI :
10.1109/DDECS.2014.6868775