Modeling timing constraints for automatic generation of embedded test instruments

This paper describes a new method to model timing constraints for the generation of basic control functions for embedded test instruments in the area of structural testing of printed circuit boards. It describes how the timing information is extracted from data sheets, modeled in a domain specific language and processed to obtain the shortest possible test time for the automatically generated embedded test instrument. The generated hardware description of the test instrument is supplied as a co-processor to an embedded test-processor. This enables the processor to access the devices-under-test with correct and optimal timing, to speed up the test process and to allow at-speed testing.