Mismatch effects and their correction in large area ASICs

Hybrid pixel detectors working in single photon counting mode are very attractive solution for new experiments as their functionality increases and the single pixel size is getting smaller. This is possible due to new deep sub-micron technologies, which allows making smaller devices. However, making smaller devices has drawbacks, one of which is that matching of smaller transistors decreases, resulting in higher offset spread of DC operating points in channels. Having large area pixel detector containing over 20.000 channels an efficient correction circuit is required in each channel allowing effective trimming of the entire matrix including small percentage of exceptional pixels. If the readout circuit contains a discriminator, different correction circuits are used for minimization of the mismatch effect usually at the discriminator input. As the pixel size is minimized correction DACs quality is often degraded and therefore it is not only non-linear but also likely non-monotonic. The large multi-thousand channel systems requires fast calculation of the correction DACs values in order to make the whole system useful. The correction scheme implemented in the large area hybrid pixel detector readout circuit containing 23552 pixels with a size of 100um × 100um each will be presented together with adequate measurements and applied correction algorithms.