On NFA-split architecture optimizations

Fast regular expression matching is widely used in many network devices. The NFA-Split hardware architecture is an efficient approach to match large set of regular expression at multigigabit speed with very low FPGA logic utilization. We propose optimizations of NFA-Split architecture, which further reduce FPGA logic utilization and significantly reduce memory utilization. The amount of utilized BlockRAMs was reduced by 97% for a Snort web-cgi module and FPGA logic utilization was reduced by 34% for a Snort backdoor module. Moreover, we propose new NFA-Split construction algorithm which decrease overall construction time up to 39 times.