DocumentCode :
1772898
Title :
Case study: BISR for a processor multiplier
Author :
Kincel, Andrej ; Balaz, Marcel
Author_Institution :
Inst. of Inf., Bratislava, Slovakia
fYear :
2014
fDate :
23-25 April 2014
Firstpage :
314
Lastpage :
317
Abstract :
The case study deals with an implementation of a built-in self-repair architecture into LEON3 processor environment. New reconfigurable logic block architecture (self-repair wrapper) of the LEON3 multiplier is designed providing self-repair ability; moreover reliability parameters (R and the mean time to failure) of the multiplier are improved as well. The test algorithm necessarily required in the self-repair procedure is also proposed. Estimations of the area overhead required for BISR, multiplier reliability parameters and fault coverage of the test algorithm are presented at the end of the paper.
Keywords :
built-in self test; integrated circuit reliability; multiplying circuits; reconfigurable architectures; BISR; LEON3 processor environment; built-in self-repair architecture; mean time to failure; multiplier; processor multiplier; reconfigurable logic block architecture; reliability parameters; Algorithm design and analysis; Circuit faults; Computer architecture; Control systems; Hardware; Reliability; Vectors; BISR; LEON3; RLB; SBST; multiplier;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
Conference_Location :
Warsaw
Print_ISBN :
978-1-4799-4560-3
Type :
conf
DOI :
10.1109/DDECS.2014.6868818
Filename :
6868818
Link To Document :
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