DocumentCode :
177295
Title :
The Dirty-Block Index
Author :
Seshadri, Vivek ; Bhowmick, Anirban ; Mutlu, Onur ; Gibbons, Phillip B. ; Kozuch, Michael A. ; Mowry, Todd C.
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2014
fDate :
14-18 June 2014
Firstpage :
157
Lastpage :
168
Abstract :
On-chip caches maintain multiple pieces of metadata about each cached block-e.g., dirty bit, coherence information, ECC. Traditionally, such metadata for each block is stored in the corresponding tag entry in the tag store. While this approach is simple to implement and scalable, it necessitates a full tag store lookup for any metadata query-resulting in high latency and energy consumption. We find that this approach is in efficient and inhibits several cache optimizations. In this work, we propose a new way of organizing the dirty bit information that enables simpler and more efficient implementations of several optimizations. In our proposed approach, we remove the dirty bits from the tag store and organize it differently in a separate structure, which we call the Dirty-Block Index (DBI). The organization of DBI is simple: it consists of multiple entries, each corresponding to some row in DRAM. A bit vector in each entry tracks whether or not each block in the corresponding DRAM row is dirty. We demonstrate the benefits of DBI by using it to simultaneously and efficiently implement three optimizations proposed by prior work: 1) Aggressive DRAM-aware writeback, 2) Bypassing cache lookups, and 3) Heterogeneous ECC for clean/dirty blocks. DBI, with all three optimizations enabled, improves performance by 31% compared to the baseline (by 6% compared to the best previous mechanism) while reducing overall cache area cost by 8% compared to prior approaches.
Keywords :
DRAM chips; cache storage; optimisation; storage management; DBI; DRAM-aware writeback; bit vector; cache lookups; cache optimizations; dirty bit information; dirty-block index; on-chip caches; tag store; Error correction codes; Indexes; Optimization; Organizations; Protocols; Random access memory; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on
Conference_Location :
Minneapolis, MN
Print_ISBN :
978-1-4799-4396-8
Type :
conf
DOI :
10.1109/ISCA.2014.6853204
Filename :
6853204
Link To Document :
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