Title :
General-purpose code acceleration with limited-precision analog computation
Author :
St. Amant, Renee ; Yazdanbakhsh, Amir ; Jongse Park ; Thwaites, Bradley ; Esmaeilzadeh, H. ; Hassibi, Arjang ; Ceze, Luis ; Burger, Danilo
Author_Institution :
Univ. of Texas at Austin, Austin, TX, USA
Abstract :
As improvements in per-transistor speed and energy efficiency diminish, radical departures from conventional approaches are becoming critical to improving the performance and energy efficiency of general-purpose processors. We propose a solution-from circuit to compiler-that enables general-purpose use of limited-precision, analog hardware to accelerate “approximable” code-code that can tolerate imprecise execution. We utilize an algorithmic transformation that automatically converts approximable regions of code from a von Neumann model to an “analog” neural model. We outline the challenges of taking an analog approach, including restricted-range value encoding, limited precision in computation, circuit inaccuracies, noise, and constraints on supported topologies. We address these limitations with a combination of circuit techniques, a hardware/software interface, neural-network training techniques, and compiler support. Analog neural acceleration provides whole application speedup of 3.7× and energy savings of 6.3× with quality loss less than 10% for all except one benchmark. These results show that using limited-precision analog circuits for code acceleration, through a neural approach, is both feasible and beneficial over a range of approximation-tolerant, emerging applications including financial analysis, signal processing, robotics, 3D gaming, compression, and image processing.
Keywords :
analogue circuits; analogue computers; energy conservation; general purpose computers; hardware-software codesign; microprocessor chips; neural chips; program compilers; algorithmic transformation; analog hardware; analog neural acceleration; analog neural model; approximable code-code; approximable regions; circuit inaccuracies; circuit techniques; compiler support; energy efficiency; energy savings; general-purpose code acceleration; general-purpose processors; hardware/software interface; limited-precision analog circuits; limited-precision analog computation; neural-network training techniques; noise; quality loss; restricted-range value encoding; topologies; transistor speed; von Neumann model; Abstracts; Analog circuits; DH-HEMTs; Hardware; Programming; Robots; Training;
Conference_Titel :
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on
Conference_Location :
Minneapolis, MN
Print_ISBN :
978-1-4799-4396-8
DOI :
10.1109/ISCA.2014.6853213