DocumentCode :
177355
Title :
Single-graph multiple flows: Energy efficient design alternative for GPGPUs
Author :
Voitsechov, Dani ; Etsion, Yoav
Author_Institution :
Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
fYear :
2014
fDate :
14-18 June 2014
Firstpage :
205
Lastpage :
216
Abstract :
We present the single-graph multiple-flows (SGMF) architecture that combines coarse-grain reconfigurable computing with dynamic dataflow to deliver massive thread-level parallelism. The CUDA-compatible SGMF architecture is positioned as an energy efficient design alternative for GPGPUs. The architecture maps a compute kernel, represented as a dataflow graph, onto a coarse-grain reconfigurable fabric composed of a grid of interconnected functional units. Each unit dynamically schedules instances of the same static instruction originating from different CUDA threads. The dynamically scheduled functional units enable streaming the data of multiple threads (or graph flows, in SGMF parlance) through the grid. The combination of statically mapped instructions and direct communication between functional units obviate the need for afull instruction pipeline and a centralized register file, whose energy overheads burden GPGPUs. We show that the SGMF architecture delivers performance comparable to that of contemporary GPGPUs while consuming ~57% less energy on average.
Keywords :
data flow computing; data flow graphs; graphics processing units; parallel architectures; power aware computing; CUDA threads; CUDA-compatible SGMF architecture; GPGPU; centralized register file; coarse-grain reconfigurable computing; coarse-grain reconfigurable fabric; compute kernel; dataflow graph; dynamic dataflow; dynamically scheduled functional units; dynamically schedules instances; energy efficient design alternative; energy overheads; full instruction pipeline; functional units; interconnected functional units; massive thread-level parallelism; single-graph multiple flows; statically mapped instructions; Computational modeling; Computer architecture; Instruction sets; Pipeline processing; System recovery;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on
Conference_Location :
Minneapolis, MN
Print_ISBN :
978-1-4799-4396-8
Type :
conf
DOI :
10.1109/ISCA.2014.6853234
Filename :
6853234
Link To Document :
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