DocumentCode
1773814
Title
An optimised processor for FMCW radar
Author
Styles, Tim ; Wildman, Leon
Author_Institution
AptCore Ltd., Bristol, UK
fYear
2014
fDate
8-10 Oct. 2014
Firstpage
497
Lastpage
500
Abstract
This paper presents a digital signal processor architecture optimized for FMCW radar systems, as used in automotive, security and surveillance applications. The novel architecture is described, along with the size, power consumption and performance for key radar processing operations. Architecture features include a flexible compute unit optimized for FFT operations and a two-dimensional register file. An FPGA implementation of the processor is used to demonstrate range-Doppler processing in real-time.
Keywords
CW radar; Doppler radar; FM radar; digital signal processing chips; fast Fourier transforms; field programmable gate arrays; power consumption; radar signal processing; FFT operations; FMCW radar system; FPGA implementation; digital signal processor architecture; power consumption; radar processing operations; range-Doppler processing; surveillance applications; two-dimensional register file; Computer architecture; Frequency modulation; Frequency-domain analysis; Radar applications; Radar signal processing; Registers; Application specific integrated circuits; Digital signal processors; Radar signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Radar Conference (EuRAD), 2014 11th
Conference_Location
Rome
Type
conf
DOI
10.1109/EuRAD.2014.6991316
Filename
6991316
Link To Document