An based-FPGA dynamic power management technique for wireless sensor network

Technologies like FPGA appear with features to be explored as implementation of low-power system. In this project we built a low-power circuit applying the implementation of a technique to minimize the clocks domains of the circuit. The architecture built has all the necessary features to integrate, synchronize and perform communication according to the application. Also a balanced operation mode among performance, reliability in the communication and power consumption for sensor nodes on FPGA is achieved. The architecture described is proposed and evaluated in an eASIC Nextreme-2 architecture, only the full-operation mode is discussed.