DocumentCode
1774577
Title
DSP-based interleaved buck power factor corrector
Author
Yu-Chen Liu ; Tsan Chen ; Po-Jung Tseng ; Yu-Kang Lo ; Huang-Jen Chiu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
fYear
2014
fDate
18-21 May 2014
Firstpage
2810
Lastpage
2814
Abstract
An interleaved Buck PFC with digital and clamping current control is proposed in this paper. Inductor current can be operated in CCM or DCM, which depends on different input line voltages and load conditions. The interleaved topology is composed of two Buck converters, which can have higher power density, lower input and output ripple currents and improve input current harmonics. Microprocessor TMS320X228035 is adopted to be the controller to implement clamping current mode control and raise the PF value at universal input. And the phase management can be adopted to lift light-load efficiency. A 300-W/80V-output digital interleaved Buck PFC with universal input and light-load efficiency all greater than 95.5% is implemented. When input voltage is over 115Vrms, the mid-to-full load PF values are all greater than 0.94.
Keywords
PWM power convertors; digital control; digital signal processing chips; electric current control; inductors; power factor correction; topology; CCM; DCM; DSP-based interleaved buck power factor corrector; PF value; TMS320X228035; buck converters; clamping current control; clamping current mode control; current harmonics; digital control; digital interleaved Buck PFC; inductor current; interleaved topology; phase management; power 300 W; voltage 80 V; Clamps; Educational institutions; Logic gates; Registers; Solids;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 International
Conference_Location
Hiroshima
Type
conf
DOI
10.1109/IPEC.2014.6870079
Filename
6870079
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