A high speed programmable frequency divider

The design of a programmable frequency divider based on a pulse swallow counter is presented to meet the requirement of high speed working. An improved and optimized dual-modulus prescaler which is the core of the divider is proposed for trade-off between high speed and low power. The divider is fabricated in SMIC 0.18μm CMOS process, and the calculation and simulation results indicate its minimum division ratio is 307 while the maximum one is 1074. Simulations with Candence Spectre show the divider can operate upto 5GHz and the total current is only 1.94mA at the highest operation frequency and 308 division ratio.