Effects of signal line references on non-ideal ground plane

In the design process of mixed-signal circuit, it is sometimes inevitable to meet partition of reference plane or slots on reference plane for the insulation of noise caused by different voltage level or IC´s different noise susceptibility. This paper studies the undesired signal integrity problems caused by single-ended signal references on this kind of non-ideal ground plane. Firstly, a typical circumstance that single-ended microstrip line crosses split ground plane is modeled. Then, slots of varying length are studied in frequency domain with application of FEM method, how length of slots on reference plane affects signal integrity on microstrip line is analyzed thoroughly. Then, a time-domain model describes situation that single-ended signal line references on ground plane with slots is built. Time-domain characteristics such as reflection, overshoot, undershoot, ringing and eye diagram are studied in depth, slots of varying length are also studied in time domain. Several novel empirical conclusions are made through numerical simulation on frequency domain and time domain which are pragmatic for the design and model of mixed signal circuit.