Performance evaluation of multi-gate fets using the BSIM-CMG model

In this paper, different multi-gate transistor configurations are analyzed using the BSIM-CMG model with emphasis on performance scaling with parameter changes. We examine the effect of key parameters on the leakage current, delay and dynamic power for basic logic gates and the mirror adder. Simulation results indicate a linear increase in the leakage current and the dynamic power with increasing number of fins. On the other hand, with larger number of gates, the static current decreases. Minimum static power dissipation can be achieved with high number of gates and a lesser number of fins.