Leakage power reduction in data driven dynamic logic circuits

In this paper, data-driven dynamic logic and its´ variant split-path data-driven dynamic logic circuits are analyzed for dynamic and static power consumption. A new low-power methodology is introduced in order to reduce the leakage current while maintaining the speed advantages of the data driven dynamic logic. A sleep switch transistor is used in the data driven dynamic circuits in order to force a sleep mode asynchronously. An additional power gating transistor is used to avoid the possible short-circuit paths during idle mode. The proposed circuits are compared against the conventional dynamic logic that uses dual-Vt sleep switch transistors for reduced leakage. 45nm technology has been used to implement the designs and they have been tested using ripple carry adders. The results demonstrate that, with the proposed circuits, leakage power can be reduced by more than 90%, with minimal impact on the speed and dynamic power consumption. Split-path data-driven dynamic logic offers the best speed and power-delay product among the dynamic logic circuits.