DocumentCode :
1776172
Title :
Floating point hardware and software realization for adaptive FIR fetal ECG estimation
Author :
Sizhou Wang ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technolog, Chicago, IL, USA
fYear :
2014
fDate :
5-7 June 2014
Firstpage :
294
Lastpage :
297
Abstract :
This paper presents realizations of IEEE-754 single precision floating point non-invasive fetal ECG estimation based on QR Decomposition Recursive Least Square algorithm (QRD-RLS). Experiments of the system, which is implemented on Xilinx Zynq SoC platform, are carried out with electrocardiogram (ECG) data and the results with analysis are presented. The embedded system design aims for hardware optimization by saving arithmetic resources, streaming pipeline performance and software-aid computation and integration. The challenge of exploiting the system full potential with pseudo-parallel computation on multiple fetal ECG data packets is also examined.
Keywords :
FIR filters; electrocardiography; least squares approximations; medical signal processing; parallel processing; system-on-chip; IEEE-754 single precision floating point; QR decomposition recursive least square algorithm; QRD-RLS algorithm; Xilinx Zynq SoC platform; adaptive FIR fetal ECG estimation; arithmetic resources; electrocardiography; embedded system design; fetal ECG data packets; finite impulse response filtering; floating point hardware; pipeline performance; pseudo-parallel computation; software realization; software-aid computation; software-aid integration; system-on-chip; Electrocardiography; Equations; Estimation; Finite impulse response filters; Hardware; Software; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electro/Information Technology (EIT), 2014 IEEE International Conference on
Conference_Location :
Milwaukee, WI
Type :
conf
DOI :
10.1109/EIT.2014.6871780
Filename :
6871780
Link To Document :
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