Design metrics improvement of 10TSRAM cell using CNFET

Author

Sinha, Aloka ; Anand, Nitin ; Islam, Aminul

Author_Institution

Dept. of Electron. & Commun. Eng., Birla Inst. of Technol., Ranchi, India

fYear

2014

fDate

10-11 July 2014

Firstpage

317

Lastpage

321

Abstract

This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (T_RA) and Write Access Time (T_WA) respectively. The proposed bit cell also offers 1.94× and 5.8× improvements in T_RA and T_WA variability respectively compared to its MOSFET counterpart. Moreover, our bit cell exhibits 39% higher read static noise margin (RSNM) and 7% higher write static noise margin @ 800 mV.

Keywords

MOSFET circuits; Monte Carlo methods; SRAM chips; carbon nanotube field effect transistors; integrated circuit design; integrated circuit noise; silicon; CNFET; MOSFET; Monte Carlo simulations; RSNM; SRAM cell; Si; bit cell; carbon nanotube field effect transistors; read access time; read static noise margin; voltage 800 mV; write access time; CMOS integrated circuits; CNTFETs; Integrated circuit modeling; MOSFET; Noise; SRAM cells; Threshold voltage; CMOS; CNFET; Read Delay; Read SNM; Write Delay; Write SNM;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on

Conference_Location

Kanyakumari

Print_ISBN

978-1-4799-4191-9

Type

conf

DOI

10.1109/ICCICCT.2014.6992977

Filename

6992977