Title :
ASIC implementation of physical downlink shared channel for LTE
Author :
Digish, K.G. ; Thilagavathy, R.
Author_Institution :
Dept. of ECE, Nat. Inst. of Technol. Tiruchirappalli, Tiruchirappalli, India
Abstract :
Long Term Evolution (LTE) is a paradigm for mobile communication providing high speed data. The LTE terms provide a framework for enlarged capacity, enhanced spectrum efficiency and coverage as well as condensed latency as compared to the second and third generation wireless networks. Six downlink channels are used by LTE of which three are data bearing channels and the rest are control channels. Physical Downlink Shared Channel (PDSCH) is the key among the data channels. The paper discusses the AS IC realization of PDSCH transmitter architecture consisting of addition of Cyclic Redundancy Check bits, channel coding, rate matching, scrambling, modulation, precoding and mapping to resource element as well as the receiver architecture comprising of resource element demapping, Multiple Input Multiple Output receiver processing, demodulation, descrambling, rate de-matching and channel decoding. The channel coding used is turbo coding and the turbo coding is realized using Maximum a-posteriori probability algorithm. The modulation schemes used are QPSK, 16-QAM and 64 QAM. The transmitter and receiver architectures are implemented for the aforesaid modulation schemes and the differences are compared. The tools used for implementation purpose are Xilinx IS E 14.2 and ISim both of which are provided by Xilinx and for synthesis and layout, tools provided by Cadence such as RTL compiler and Encounter were used.
Keywords :
Long Term Evolution; MIMO communication; application specific integrated circuits; channel coding; cyclic redundancy check codes; maximum likelihood estimation; precoding; probability; quadrature amplitude modulation; quadrature phase shift keying; radio receivers; radio transmitters; wireless channels; 16-QAM; 64 QAM; ASIC implementation; Cadence; ISim; LTE; Long Term Evolution; PDSCH; QPSK; RTL compiler; Xilinx ISE 14.2; channel coding; channel decoding; cyclic redundancy check bit; data bearing channel; demodulation; descrambling; enhanced spectrum efficiency; maximum a-posteriori probability algorithm; mobile communication; modulation; multiple input multiple output receiver processing; physical downlink shared channel; precoding; rate dematching; rate matching; receiver architecture; resource element demapping; resource element mapping; scrambling; second generation wireless network; third generation wireless network; transmitter architecture; turbo coding; Decoding; Downlink; Phase shift keying; Receivers; Transmitters; Turbo codes; LTE; Mapping to Resource Element; Modulation; Multiple Input Multiple Output receiver processing; PDSCH; Precoding; Scrambling; synthesis;
Conference_Titel :
Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4799-4191-9
DOI :
10.1109/ICCICCT.2014.6992989