Modified Viterbi decoder for HMM based speech recognition system

Viterbi algorithm is a dynamic programming algorithm used to find out the most likely word uttered by the unknown speech signal. In Viterbi algorithm, the observation probabilities are calculated using Gaussian distribution function. For implementation of Viterbi decoder, these probability values are initially stored in RAM. Thus conventional Viterbi decoder requires large RAM for its execution. In this paper, architecture for log Gaussian function has been designed and described using verilog for FPGA implementation. This proposed log Gaussian enables the system to calculate the observation probabilities dynamically for the unknown speech signal without storing them in internal memory. The proposed architecture use logarithm base 2 function for its implementation. An algorithm for implementing of Log_2 for 16 bit floating point is also presented in this paper. IEEE-754 16 bit Binary Floating point Adder and Multiplier are designed to perform all the calculations in Verilog. All the design modules are implemented in Xilinx 12.2 and successfully synthesized on Virtex5 FPGA.