Title :
Implementation of 32-bit area-efficient hybrid modulo 2n+1 adder and multiplier
Author :
Asha, G.H. ; Uday, J.
Author_Institution :
Malnad Coll. of Eng., Visvesvaraya Technol. Univ., Belgaum, India
Abstract :
Modular addition and multiplication plays an important role in data encryption standard. In this paper a new VLSI circuit architectures for addition and multiplication of modulo 2n+1 are presented, which allows the implementation of highly efficient combinational circuits for modular arithmetic. The architecture for adder and multipliers are based on Diminished-1 representation. To realize the architecture we use area efficient Hybrid parallel-prefix adder by using a new prefix operator known as O3-black operator and Sparse carry computation unit. The architectures are implemented on Xilinx Spartan III field-programmable gate array (FPGA) using ISE 14.3. The results indicate that, on an average, the implemented architectures are better in terms of slices, LUT´s and memory utilization by comparing all formal proposals.
Keywords :
VLSI; adders; combinational circuits; digital arithmetic; field programmable gate arrays; multiplying circuits; FPGA; ISE 14.3; O3-black operator; VLSI circuit architectures; Xilinx Spartan III field-programmable gate array; area efficient hybrid parallel-prefix adder; combinational circuits; diminished-1 representation; modular addition; modular arithmetic; modular multiplication; modulo 2n+1 adder; modulo 2n+1 multiplier; prefix operator; sparse carry computation unit; Adders; Computer architecture; Educational institutions; Equations; Instruments; Mathematical model; Wiring; Diminished-1 Adders; Hybrid Parallel Prefix adders; O3-black; Sparse;
Conference_Titel :
Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4799-4191-9
DOI :
10.1109/ICCICCT.2014.6993042