Implementation of 32-bit area-efficient hybrid modulo 2n+1 adder and multiplier

Modular addition and multiplication plays an important role in data encryption standard. In this paper a new VLSI circuit architectures for addition and multiplication of modulo 2ⁿ+1 are presented, which allows the implementation of highly efficient combinational circuits for modular arithmetic. The architecture for adder and multipliers are based on Diminished-1 representation. To realize the architecture we use area efficient Hybrid parallel-prefix adder by using a new prefix operator known as O3-black operator and Sparse carry computation unit. The architectures are implemented on Xilinx Spartan III field-programmable gate array (FPGA) using ISE 14.3. The results indicate that, on an average, the implemented architectures are better in terms of slices, LUT´s and memory utilization by comparing all formal proposals.