Synchronous elastic circuit with higher throughput at reduced area and power

To reduced area and power in synchronous elastic circuits we are using combinations of various elasticity approaches. Elasticity refers to the property of a circuit in which circuits can tolerate arbitrary latency/delay variations in their computation units as well as communication channels. Elasticity does not make any assumption about the specific implementation of the circuit. This paper investigates different optimization approaches to reduce these area and power overheads of elastic control network without sacrificing the control network performance. Ultra simple fork (USFork), early evaluation join (EEJoin), half-buffer retiming (HBR) controller, eager Fork, join, lazy fork combinations for implementation are introduced. In this approach we check all node and all combinational blocks clock period and uses elastic buffer only when it needed. Comparing to published work on a Minimips processor case study[3] and Synchronous elasticization at reduced cost[2], our implementation shows up 8% and 15.08% area and power due to proposed flow of implementing synchronous elasticization with 17.5 % increase in throughput i.e. 0.94 Gbits/sec.