Design of fast and efficient 1-bit full adder and its performance analysis

Author

Shinde, Kunjan D. ; Nidagundi, Jayashree C.

Author_Institution

Dept. of E&CE, S.D.M. Coll. of Eng. & Technol., Dharwad, India

fYear

2014

fDate

10-11 July 2014

Firstpage

1275

Lastpage

1279

Abstract

The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed on Cadence Design Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm technology with a unvaried width and length of PMOS and NMOS devices. The paper gives a compression of various design of 1 bit full adder with respect to number of transistors/ gate count, Delay, Power and Power Delay Product.

Keywords

adders; logic design; ADE environment; Cadence Design Suit 6.1.5; GPDK; NMOS device; PMOS device; Virtuoso; binary adders; binary addition; computational process; digital system; full adders; gate count; half adder; performance analysis; power delay product; Adders; CMOS integrated circuits; Delays; Logic gates; MOS devices; Simulation; Transistors; CMOS; Delay; Full Adder; GDI; GDI-PTL; No. of Transistors/Gate count; Power and PDP; TG;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on

Conference_Location

Kanyakumari

Print_ISBN

978-1-4799-4191-9

Type

conf

DOI

10.1109/ICCICCT.2014.6993157

Filename

6993157