Improved analytical potential modeling in double-gate tunnel-FETs

In the last few years, the Tunnel-FET has become one of the promising devices to be the successor of the MOSFET due to its CMOS compatibility and steep subthreshold slopes (S) below 60 mV/dec. The rapid forthcoming of research regarding the Tunnel-FET leads to a wide range of studied device geometries, different hetero-structure combinations and applied technological methods. All with the aim of improving the device ON-state current and subthreshold slope. In order to accurately model this Tunnel-FET variety a precise potential model of the whole device is inevitable. This work shows an improved two-dimensional closed-form potential model applying the conformal mapping technique. To validate the model, all results are compared against TCAD Sentaurus simulation data.