Title :
A novel method in fractional synthesizers for a drastic decrease in lock time
Author :
Ghasemzadeh, Mehdi ; Akbari, Amin ; Mohabbatian, Neda ; Hadidi, Khayrollah ; Khoei, Abdullah
Author_Institution :
Microelectron. Res. Lab., Urmia Univ., Urmia, Iran
Abstract :
A 1GHz frequency divider is presented in this paper. The proposed architecture aims to minimize lock time in Phase-Locked Loops (PLLs). Proposed structure has been simulated by HSPICE software in a typical 0.18μm CMOS technology at the supply voltage of 1.8V. Simulation results show that the designed divider locks in 2-20μs which is a lower lock time compared to conventional PLLs.
Keywords :
CMOS integrated circuits; UHF frequency convertors; UHF integrated circuits; frequency dividers; frequency synthesizers; phase locked loops; voltage-controlled oscillators; CMOS technology; HSPICE software; PLLs; fractional synthesizers; frequency 1 GHz; frequency divider; lock time minimization; phase-locked loops; size 0.18 mum; time 2 mus to 20 mus; voltage 1.8 V; voltage control oscillator; Integrated circuits; Phase-Locekd Loop; Voltage Control Oscillator; jitter; lock time;
Conference_Titel :
Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference
Conference_Location :
Lublin
Print_ISBN :
978-83-63578-03-9
DOI :
10.1109/MIXDES.2014.6872173
