Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS

Author

Dasgupta, Roma ; Bugiel, Szymon ; Glab, Sebastian ; Idzik, Marek ; Moron, Jakub ; Kapusta, Piotr

Author_Institution

AGH Univ. of Sci. & Technol., Cracow, Poland

fYear

2014

fDate

19-21 June 2014

Firstpage

175

Lastpage

179

Abstract

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; silicon-on-insulator; SAR ADC; frequency 20 MHz; parasitic capacitances; power consumption; power dissipation; silicon-on-insulator; size 200 nm; sub-micron SOI CMOS technology; successive approximation register analog-to-digital converter; voltage 1.8 V; word length 10 bit; CMOS integrated circuits; CMOS technology; Capacitance; Clocks; Power demand; Silicon-on-insulator; Switches; SAR ADC; SOI; merge capacitor switching; nonredundant control logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference

Conference_Location

Lublin

Print_ISBN

978-83-63578-03-9

Type

conf

DOI

10.1109/MIXDES.2014.6872180

Filename

6872180