Design of a reference voltage buffer for a 10-bit 1-MS/s SAR ADC

The paper presents the design of a single-ended amplifier in 1.8 V, 180 nm CMOS process for buffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffer such as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation achieves worst-case settling time of 19.3 ns and current consumption of 66 μA while occupying an area of (19.2 μm × 19.2 μm).