Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET)

Author

Pfitzner, Andrzej

Author_Institution

Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland

fYear

2014

fDate

19-21 June 2014

Firstpage

323

Lastpage

327

Abstract

In this paper a simple compact DC model of junction-less twin-gate Vertical-Slit Field-Effect Transistor (VeSFET) has been developed*. This device is the elementary component of a new 3D VeSTIC technology [1]. Feasibility studies conducted until now, confirm the attractive electrical properties of VeSFETs and indicate that VeSTIC architecture has the potential to overcome many barriers of ICs scaling in the deep-submicron era. The first, rudimentary compact DC model provided in [5] combined physical description with empirical formulas. That model has been improved here to considerably reduce the number of fitting parameters, retaining high accuracy. Good universality of the model was verified for various geometric and material parameters of the VeSFET structure.

Keywords

field effect transistors; semiconductor device models; 3D VeSTIC technology; ICs scaling; VeSFET; electrical properties; fitting parameters; junction-less twin-gate vertical-slit field-effect transistor; rudimentary compact DC model; vertical-slit field-effect transistor; Accuracy; Integrated circuit modeling; Logic gates; Mathematical model; Numerical models; Threshold voltage; Transistors; VeSFET; VeSTIC technology; Vertical-Slit Field-Effect Transistor; compact model; junction-less transistor; twin-gate transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference

Conference_Location

Lublin

Print_ISBN

978-83-63578-03-9

Type

conf

DOI

10.1109/MIXDES.2014.6872210

Filename

6872210