Design of radial nanowire tunnel field-effect transistors

The package density is one main motivation for transistor scaling. It has been suggested that alternative paths need to be considered for scaling of future high-speed low-power devices. For this reason, we consider tunnel field-effect transistors as a radial device in a vertical nanowire architecture. TFETs have already been demonstrated with metal-oxide-semiconductor field-effect transistor (MOSFET) like current levels. The benefit of a vertical nanowire architecture is to enable high drive currents without sacrificing neither the chip area footprint nor the device electrostatics. In this paper, we explore the key elements of a radial tunnel field-effect transistor (rTFET) and the impact on the device performance based on experimental data from both Esaki diodes and TFETs in a radial nanowire architecture.