Enhanced hole mobility of Ge/GeSn pMOSFETs with a GeSnO interface layer and a NiGe Schottky source/drain

As the dimensions of MOSFETs continue to scale down, high-k dielectrics are being used to reduce gate leakage currents, and high-mobility semiconductors such as Ge are promising channel materials for increasing the operating speed of the devices [1]. However, poor Ge/high-k interface properties and the tendency to fabricate an ultra shallow source/drain (S/D) with low series resistance are two major problems for Ge MOSFETs [2]. In our previous work, we demonstrated that a GeSnO interlayer is an effective passivation method [3]. In this paper, we report the realization of Ge/GeSn pMOSFETs featuring an advanced gate stack process with a GeSnO interface layer and an implantless metallic NiGe Schottky S/D. Experimental results show that the fabricated Ge/GeSn MOS devices exhibit promising characteristics, and an approximately 3-fold hole-mobility enhancement is achieved compared with Si universal mobility. These results demonstrate that introducing a GeSn/GeSnO layer can benefit carrier mobility. Superior interface quality and the induced stress in Ge wafers may be responsible for the mobility enhancement.