Title :
Epitaxial rare earth oxide (EOx) FinFET: A variability-resistant Ge FinFET architecture with multi VT
Author :
Mittal, Sparsh ; Kurude, S. ; Dutta, Suparna ; Debashis, Punyashloka ; Ganguly, Shaumik ; Lodha, Saurabh ; Laha, A. ; Ganguly, Utsav
Author_Institution :
Dept. of EE, Indian Inst. of Technol. Bombay, Mumbai, India
Abstract :
Band to band tunneling (BTBT) is a major challenge in Ge FinFETs due to its smaller band gap. Reduction in BTBT by quantum-confinement (QC) based increase in band-gap requires narrow Wfin. However, Line Edge Roughness (LER) on narrow fins causes large VT variability. Improved fin-width process e.g. SADP [1], ALE [2] have been proposed to reduce LER. Alternatively, variability resistant transistor design has been recently proposed with thin Ge on Si highly retrograde doped fins by our group [3], which also provides multiple VT capability - a major challenge in FinFETs. However, this has 2 challenges - (i) thickness limitation of <; 2nm of defect-free Ge on Si and (ii) RDF in the retrograde doped fins. In this study, we propose a dual-gate structure like FinFET by epitaxially growing undoped Ge /rare earth oxide (e.g. Gd2O3) [4] stack on highly doped Si fins. By statistical simulations, we show that this structure can reduce LER based variability by more than 90% in comparison to FinFETs at a similar performance. RDF is negligible due to the undoped Ge channel. Thicker (>2nm) defect-free Ge can be grown epitaxially on Gd2O3 [4]. We show the multi-VT capability enabled by independent back-gate biasing, and hence provides a significant advantage over FinFETs. Experimental data from MOSCAP with epi Gd2O3 as gate dielectric (~ 4.5 nm) show lower leakage currents than LSTP specification.
Keywords :
MOSFET; elemental semiconductors; epitaxial growth; germanium; semiconductor epitaxial layers; semiconductor growth; statistical analysis; BTBT; EOx FinFET; Ge; LER; MOSCAP; QC; RDF; Si; band gap; band to band tunneling; dual-gate structure; epitaxial rare earth oxide; gate dielectric; improved fin-width process; independent back-gate biasing; leakage currents; line edge roughness; multithreshold voltage; quantum-confinement; statistical simulations; variability resistant transistor design; variability-resistant FinFET architecture; Epitaxial growth; FinFETs; Leakage currents; Logic gates; Mathematical model; Semiconductor process modeling; Silicon;
Conference_Titel :
Device Research Conference (DRC), 2014 72nd Annual
Conference_Location :
Santa Barbara, CA
Print_ISBN :
978-1-4799-5405-6
DOI :
10.1109/DRC.2014.6872315