DocumentCode :
1777293
Title :
Electrostatically doped WSe2 CMOS inverter
Author :
Das, S. ; Roelofs, Andreas
Author_Institution :
Center for Nanoscale Mater., Argonne Nat. Lab., Argonne, IL, USA
fYear :
2014
fDate :
22-25 June 2014
Firstpage :
185
Lastpage :
186
Abstract :
In this article we report a fully complementary CMOS inverter using multi-layer WSe2 as the channel material in dual gated transistor geometry. We have employed electrostatic doping and contact work function engineering in order to experimentally demonstrate the logic inverter. The maximum inverter gain was found to be ~12. The noise margin (NM) was ~ 2.0V. Semiconducting transition metal dichalcogenides (TMDs) like MoS2, MoSe2, WSe2 and many others are being investigated as potential candidates for beyond Si nanoelectronics owing to their ultra-thin body that allow aggressive channel length scaling (1-4). In this context, it is important to demonstrate simple logic circuits like the inverter with these novel 2D crystals in order to justify their true potential. An inverter should ideally comprise of a PFET and an NFET with similar drive current capabilities. This requires that the channel material should provide easy access to both the electron in the conduction band and holes in the valence band. In Si CMOS this feature is easily achieved through substitutional doping. However, in case of the TMDs, due to the absence of a controllable and sustainable doping scheme, one has to rely on electrostatic doping (adjustment of threshold voltage through gating) and the position of contact Fermi level determined by the work function of the contact metal to enable electron or hole conduction.
Keywords :
CMOS logic circuits; conduction bands; electrostatics; logic gates; molybdenum compounds; tungsten compounds; valence bands; work function; 2D crystals; MoS2; MoSe2; NFET; NM; PFET; TMDs; WSe2; aggressive channel length scaling; channel material; conduction band; contact Fermi level; contact metal; contact work function engineering; dual gated transistor geometry; electron conduction; electrostatic doping; electrostatically doped CMOS inverter; fully complementary CMOS inverter; hole conduction; logic circuits; logic inverter; noise margin; semiconducting transition metal dichalcogenides; silicon nanoelectronics; sustainable doping scheme; valence band; Doping; Inverters; Logic gates; Materials; Metals; Threshold voltage; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference (DRC), 2014 72nd Annual
Conference_Location :
Santa Barbara, CA
Print_ISBN :
978-1-4799-5405-6
Type :
conf
DOI :
10.1109/DRC.2014.6872359
Filename :
6872359
Link To Document :
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