III-V Gate-wrap-around field-effect-transistors with high-k gate dielectrics

As MOSFETs continue scaling down for low power logic applications, non-planar multi-gated field-effect-transistors have been brought out to overcome the electrostatics control issue. To achieve the ultimate gate electrode control, great efforts have been devoted to investigate nanowire and GWAFETs or gate-all-around (GAA) FETs devices. Nanowires can be constructed using bottom-up synthesis method where various materials can be used but huge manufacture challenges, or by top-down machining approach. The gate-wrapped-around structure was applied to higher-electron-mobility III-V material in order to achieve a combination of improved subthreshold characteristics and higher current drive capability. Much works on III-V multi-gated FETs and GWAFETs have shown promising results including better SCE control and increased integration density. However, several challenges remain, such as current degradation from quantum effect, leakage current, high-k/III-V interface quality, external contact resistance, and fabrication difficulties. In this work, we fabricated the lateral In_0.53Ga_0.47As GWAFETs using the top-down method, that is, the devices were patterned by e-beam lithography and nanowires were constructed by dry and wet etching process. We will present (a) novel device and layout design such that the resulting fin structure is more robust, (b) an optimized fin-etching process in order to achieve smooth sidewalls of the InGaAs channels, (c) high-quality high-k dielectrics and metal gate stack to enhance the interface and bulk oxide quality and (d) device modeling and simulation results to explain device characteristics. The layer structure of In_0.53Ga_0.47As GWAFET device, grown by MBE on the semi-insulating InP substrate, consists of 500 nm InP buffer layer, 50 nm In_0.53Ga_0.47As channel layer, 1 nm InP barrier layer and 20 nm In_0.53Ga_0.47As cap layer. All these layers were designed to - e undoped, except for the top In_0.53Ga_0.47As layer which is a heavily N-doped (Si 3e19cm^-3) layer intended for source/drain (S/D) contact. Fig. 1 illustrates the device layer structure of In_0.53Ga_0.47As GWAFET with the channel wrapped around by ALD Al₂O₃/TiN gate. InP was chosen as the buffer layer to enable selective wet etch between In_0.53Ga_0.47As and InP for releasing the In_0.53Ga_0.47As fin structure. The key fabrication steps and improved layout design are illustrated in Fig. 2 and 3, respectively. The transfer characteristics of a typical In_0.53Ga_0.47As GWAFET with W_fin=40 nm, L_g=140 nm, and 7 parallel channels demonstrate excellent behavior (Fig. 4). Drive currents are normalized to the perimeter of InGaAs channels W_tot = (2W_fin+2H_fin)×(No. of channels). The gate leakage is lower than 10^-5 μA/μm in the voltage range. The on/off current ratio of this device is around 4×10⁴ at V_d=1 V. The off current is at 2×10^-3 μA/μm level at V_g=-0.2 V and V_ds=0.5 V. The off current is limited by the bulk leakage current. Detailed device characteristics will be shown in the presentation. Fig. 4 illustrates the I_d-V_g characteristics of InGaAs planar MOSFETs and non-planar InGaAs GWAFETs. 10X drop on DIBL was observed from planar InGaAs MOSFETs at around 200mV/V to 20mV/V for GWAFETs. By apply gate wrapped around structure SS also reduced 33%. Fig. 5 shows the DIBL vs. gate length for 10 nm, 5 nm-thick InGaAs channel MOSFETs and InGaAs GWAFETs with W_fin 200 nm, 100 nm, 60 nm and 40 nm. Better scalability was achieved by non-planar GWAFETs compare to planar structure with lower DIBL, SS and higher drive current.