• DocumentCode
    1777330
  • Title

    Vertical electron transistors with In0.53Ga0.47As channel and N-polar In0.1Ga0.9N/GaN drain achieved by direct wafer-bonding

  • Author

    Jeonghee Kim ; Lal, Sunil ; Laurent, Matthew A. ; Mishra, Umesh K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
  • fYear
    2014
  • fDate
    22-25 June 2014
  • Firstpage
    221
  • Lastpage
    222
  • Abstract
    The design space of conventional semiconductor devices - from the materials point of view - is currently set by heteroepitaxy, whose capability is strongly limited by lattice parameters and structures of materials of interest. Heterostructures of substantially different semiconductors may offer significant advantages in device design, but many of them are likely heteroepitaxy-incompatible. In such cases, direct wafer-bonding can be exploited, in which materials of interest are separately grown and then their heterostructures formed by thermo-compression. InGaAs, with its superior electron mobility and injection velocity, is considered as the best candidate material for achieving electronic devices in THz applications, whereas III-N has proven its promise in high-power applications. Thus, transistors consisting of InGaAs channel and III-N drain may potentially attain both the high-speed and high-power performances. The first bonded aperture vertical electron transistor (BAVET) with In0.53Ga0.47As channel and Ga-polar InGaN/GaN drain was demonstrated in 2009 [1], and further improvements on it have also been reported [2], [3]. Here, we demonstrate the first BAVET consisting of In0.53Ga0.47As channel and N-polar In0.1Ga0.9N/GaN drain, which has an inherent advantage over Ga-polar InGaN/GaN drain, as discussed below.
  • Keywords
    III-V semiconductors; electron mobility; gallium arsenide; indium alloys; power transistors; transistors; wafer bonding; wide band gap semiconductors; BAVET; III-N drain; In0.1Ga0.9N-GaN; In0.53Ga0.47As; N-polar drain; THz applications; bonded aperture vertical electron transistor; device design; direct wafer-bonding; electron mobility; electronic devices; heteroepitaxy; high-speed high-power performance; injection velocity; lattice parameter; semiconductor device design space; semiconductor heterostructures; thermo-compression; vertical electron transistors; Gallium nitride; Gate leakage; Indium gallium arsenide; Logic gates; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference (DRC), 2014 72nd Annual
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    978-1-4799-5405-6
  • Type

    conf

  • DOI
    10.1109/DRC.2014.6872377
  • Filename
    6872377