Measurement and analysis of gate-induced drain leakage in short-channel strained silicon germanium-on-insulator pMOS FinFETs

Strained silicon germanium (s-SiGe) pMOS finFETs have proven benefits over silicon p-MOSFETs due to their superior transport properties which is attributed to uniaxial stress-induced lower hole effective mass [1-2]. However, the narrower bandgap of SiGe compared to silicon leads to an increase in band-to-band tunneling, which results in higher gate-induced drain leakage (GIDL). Previous work has focused on understanding long-channel GIDL for planar buried-channel s-SiGe pFETs with Si cap and ion-implanted source/drain [3,4]. In this work, for the first time, we investigate the short channel GIDL characteristics of surface-channel strained-Si_1-xGe_x (x=0.27 and 0.5) p-MOSFETs in a finFET architecture using a Si-cap-free surface passivation and ion implant-free raised S/D process. We show devices having a minimum GIDL current of 1nA/um for x=0.27 and 20nA/um for x=0.5 at an operating voltage of V_DD=0.8V and an operating temperature of 50°C. In addition, temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling (BTBT) is the dominant leakage mechanism as compared to trap-assisted tunneling (TAT) for both cases.