Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects

Probabilistic behavior of logic gates represents one of the main reliability problems associated to CMOS circuits supplied at very low supply voltages. This paper aims to analyze the impact of probabilistic faults in interconnects, by means of HDL saboteur-based simulated fault injection (SFI). We propose four types of saboteurs: the simplistic probabilistic type, a switching type - aware and two data dependent types. We have analyzed the behavior of the Wishbone bus in the presence of probabilistic errors. Several sets of simulations have been performed, by injecting probabilistic faults on address, control signals and data components of the bus. The performed simulations indicate that the simulation time for a SFI campaign is 1.7× higher with respect to the gold circuit.